Microarchitecture is undergoing dramatic yet exciting changes in light of a number of “show–stopper” problems in the design and evaluation of future digital systems. These problems include the emergence of chip multiprocessors as the architecture of choice to ride the Moore's law and the lack of mainstream parallel software and programming models; the prohibitive levels of power consumption in conventional designs and the need for novel design and evaluation methodologies for power–/cost–efficient and performance-scalable implementations; and dramatic reductions in transistor and circuit reliability, testability and yield in future technologies and the need for robust and reliable microarchitecture. The work in this theme addresses these broad and critical design and evaluation challenges facing microarchitects.

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