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e-Seminar

Imperfection-Immune Digital VLSI using Carbon Nanotube Field Effect Transistors

June 11, 2010
2–3 PM EST (11 AM–12 PM PST)

Abstract

Carbon Nanotube Field Effect Transistors (CNFETs) are excellent candidates for building highly energy-efficient future systems. Despite significant progress at a single-device level, fundamental limitations inherent to carbon nanotubes (CNTs) pose major obstacles to the realization of robust CNFET-based systems:

It is nearly impossible to guarantee "perfect" alignment and positioning of all CNTs. This limitation introduces stray conducting paths, resulting in incorrect circuit functionality.
CNTs can be metallic or semiconducting depending on chirality. No known CNT growth process yields exclusively semiconducting CNTs. Metallic CNTs cause shorts resulting in excessive leakage and incorrect circuit functionality.

Today's CNT processing alone is inadequate to overcome these challenges. A combination of design and processing techniques, presented in this talk, enables VLSI-scale CNFET circuits that are immune to these inherent imperfections:

New design techniques that are immune to misaligned and mis-positioned CNTs, for all Boolean functions.
A new design technique, combined with CNT processing, guarantees correct circuits even though the CNT growth process cannot guarantee the absence of metallic CNTs.

Our imperfection-immune design techniques retain energy efficiency benefits of CNFETs, and are compatible with VLSI processing and design flows. Using these techniques, we experimentally demonstrate:

VLSI-compatible and imperfection-immune CNFET combinational circuits and sequential storage elements.
Monolithic three-dimensional CNFET ICs.

This research was performed in collaboration with Prof. H.-S.P. Wong of Stanford University (FCRP FENA) and Stanford Ph.D. students Jie Deng, Albert Lin, Nishant Patil, Hai Wei, and Jie Zhang.

Speaker

Subhasish Mitra
Stanford University

Subhasish Mitra is an Assistant Professor in the Department of Electrical Engineering and the Department of Computer Science of Stanford University where he leads the Stanford Robust Systems Group. His research interests include:

Robust system design;
VLSI design, CAD, validation and test;
Emerging nanotechnologies.

Prior to joining Stanford, he was a Principal Engineer at Intel Corporation.

Prof. Mitra has invented design and test techniques that have seen wide-spread proliferation in the semiconductor industry. His X-Compact technique for test compression is used by 50+ Intel products, and is supported by major CAD tools. His IFRA technology for post-silicon validation, jointly with his graduate student, was characterized as "a breakthrough" in a Research Highlight in the Communications of the ACM. His work on an imperfection-immune, robust carbon nanotube VLSI technology, jointly with his students and collaborators, has been highlighted as "a significant breakthrough" by the Semiconductor Research Corporation, MIT Technology Review, and as "a recent research highlight" by NSF in its report to the U.S. Congress.

Prof. Mitra's honors include the Presidential Early Career Award for Scientists and Engineers (PECASE, the highest honor bestowed by the US government on early-career outstanding scientists and engineers), NSF CAREER Award, Terman Fellowship, IEEE CAS/CEDA Pederson Award (IEEE Trans. CAD Best Paper), ACM SIGDA Outstanding New Faculty Award, IEEE/ACM Design Automation Conference Best Paper, IBM Faculty Awards, Divisional Recognition Award from Intel "for a Breakthrough Soft Error Protection Technology," and the Intel Achievement Award, Intel's highest corporate honor, "for the development and deployment of a breakthrough test compression technology." Prof. Mitra currently serves on the DARPA Information Science and Technology Board as an invited member, and on several conference committees and journal editorial boards.