June 29, 2010
4 PM EST (1 PM PST)
Flash analog-to-digital converters (ADCs) are commonly used for high-speed, low-resolution applications because of their simple and highly-parallel architecture. The number of comparators in a flash ADC increases exponentially with resolution while the input offset specification becomes exponentially smaller. To meet the offset specification with minimal power and area overhead, comparator calibration techniques are required.
This talk presents a new digital calibration technique, statistical element selection (SES). SES provides exponential decrease in offset standard deviation with respect to the total number of elements. Monte Carlo simulation results demonstrate SES and provide guidance for design efforts. Yield is shown to improve considerably faster than competing calibration techniques (DAC-based calibration, redundancy, and increased device sizing).
Two SES-based comparator designs are implemented in 65nm digital bulk CMOS. Silicon measurements verify the Monte Carlo simulation results and demonstrate significant improvements in offset standard deviation (14mV to 0.3mV) and yield (10.9% to 99.6%).
An 8-bit, 1.5GS/s flash ADC is implemented using the SES-based 65nm CMOS comparators. The performance is limited by comparator noise which degrades the effective number of bits (ENOB) from 7.5 bits to 5.8 bits. The ADC achieves a figure of merit (FoM) of 0.42pJ/conv, among the best reported for 1+ GS/s, 6- to 8-bit ADCs.
Carnegie Mellon University
Jon Proesel received the B.S. degree in computer engineering from the University of Illinois at Urbana-Champaign in 2004. He received the M.S. and Ph.D. degrees in electrical and computer engineering from Carnegie Mellon University in 2008 and 2010, respectively. In 2010 he joined the IBM T.J. Watson Research Center as a postdoctoral researcher in analog and mixed-signal circuit design for silicon integrated nanophotonics. His current research interests include data converters, optical interface circuits, and high-speed I/Os.