Center for Circuit System Solutions

News & Events

e-Seminar

Creating Chip Generators for Efficient Computing at Low NRE Design Costs

February 13, 2012
4:00 PM EST (1:00 PM PST)

e-Seminar Access

Members, log in to access the e-Seminar link.

Abstract

Recent changes in technology scaling have made power dissipation today's major performance limiter. In addition, increasing non-recurring engineering (NRE) costs are making the traditional solution to power efficiency, application specific designs, prohibitively expensive. To address this impasse, this talk proposes creating a design framework that would generate application tailored semi-custom designs. This framework is referred to as Chip Generator. The proposed chip generators codify the designer knowledge and design trade-offs about building a specific class of hardware into a flexible template that can then be used to create many different chips. For this purpose, a tool, Genesis2, was created. It extends SystemVerilog to allow designers to embed "elaboration programs" -- recipes for making the desired hardware block. Genesis2 has been used for creation of a number of digital and mixed signal chips and IP blocks at Stanford and CMU. This e-seminar will also show how the proposed approach can create floating points units which are higher performance and lower delay than the leading libraries available today. If time permits, this talk will also touch on how generators can take a common theme in RTL validation -- varying internal parameters such as FIFO or queue depths to induce functional corner cases -- to new levels, for exposing bugs orders of magnitudes faster.

Speaker
Ofer Shacham

Ofer Shacham
Stanford

Ofer Shacham is a post-doctoral researcher at Stanford University and the founder of Chip Genesis, a company that aims to commercialize the Stanford Chip Generator technologies -- technologies that enable design of more power-efficient and more NRE-cost-efficient chips. Shacham is a recent graduate of the Stanford electrical engineering PhD program, where his research interests include high performance and parallel computer architectures, and VLSI design and verification techniques. Prior to his academic career, Shacham had worked for IBM R&D Labs in Israel. Prior to that, Shacham had also served as a Sergeant Major in an elite unit in the Israeli Navy.

Semiconductor Research Corporation - Focus Center Research Program

Copyright © 2012 C2S2. All rights reserved. Site maintenance by Carnegie Mellon University ECE Web Team.